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vishay siliconix SI1315DL new product document number: 67193 s10-2765-rev. a, 29-nov-10 www.vishay.com 1 p-channel 8 v (d-s) mosfet features ? halogen-free accordin g to iec 61249-2-21 definition ?trenchfet ? power mosfet ? 100 % r g te s t e d ? compliant to rohs directive 2002/95/ec applications ? load switch for portable devices ? dc/dc converters product summary v ds (v) r ds(on) ( ? )i d (a) c q g (typ.) - 8 0.336 at v gs = - 4.5 v - 0.9 1 nc 0.450 at v gs = - 2.5 v - 0.7 0.650 at v gs = - 1.8 v - 0.5 notes: a. surface mounted on 1" x 1" fr4 board. b. t = 10 s. c. based on t c = 25 c. absolute maximum ratings (t a = 25 c, unless otherwise noted) parameter symbol limit unit drain-source voltage v ds - 8 v gate-source voltage v gs 8 continuous drain current (t j = 150 c) t c = 25 c i d - 0.9 a t c = 70 c - 0.7 t a = 25 c - 0.8 a, b t a = 70 c - 0.7 a, b pulsed drain current i dm - 3 continuous source-drain diode current t c = 25 c i s - 0.3 t a = 25 c - 0.25 maximum power dissipation t c = 25 c p d 0.4 w t c = 70 c 0.2 t a = 25 c 0.3 a, b t a = 70 c 0.2 a, b operating junction and storage temperature range t j , t stg - 50 to 150 c soldering recommendations (peak temperature) 260 orderin g information: SI1315DL-t1-ge3 (lead (p b )-free and halogen-free) top v ie w SI1315DL (lj)* * marking code sot-323 sc-70 (3-leads) 1 2 3 g s d s g d p-channel mosfet
www.vishay.com 2 document number: 67193 s10-2765-rev. a, 29-nov-10 vishay siliconix SI1315DL new product notes: a. surface mounted on 1" x 1" fr4 board. b. maximum under steady state conditions is 430 c/w. notes: a. pulse test; pulse width ? 300 s, duty cycle ? 2 %. b. guaranteed by design, not s ubject to production testing. stresses beyond those listed under ?absolute maximum ratings? ma y cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other condit ions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ratings parameter symbol typical maximum unit maximum junction-to-ambient a, b t ?? 10 s r thja 315 375 c/w maximum junction-to-foot (drain) steady state r thjf 285 340 specifications (t j = 25 c, unless otherwise noted) parameter symbol test conditions min. typ. max. unit static drain-source breakdown voltage v ds v gs = 0 v, i d = - 250 a - 8 v v ds temperature coefficient ? v ds /t j i d = - 250 a - 7.6 mv/c v gs(th) temperature coefficient ? v gs(th) /t j 2.0 gate-source threshold voltage v gs(th) v ds = v gs , i d = - 250 a - 0.4 - 0.8 v gate-source leakage i gss v ds = 0 v, v gs = 8 v 100 na zero gate voltage drain current i dss v ds = - 8 v, v gs = 0 v - 1 a v ds = - 8 v, v gs = 0 v, t j = 55 c - 10 on-state drain current a i d(on) v ds ? - 5 v, v gs = - 4.5 v - 2 a drain-source on-state resistance a r ds(on) v gs = - 4.5 v, i d = - 0.8 a 0.280 0.336 ? v gs = - 2.5 v, i d = - 0.5 a 0.375 0.450 v gs = - 1.8 v, i d = - 0.3 a 0.500 0.650 forward transconductance a g fs v ds = - 5 v, i d = - 0.8 a 3s dynamic b input capacitance c iss v ds = - 4 v, v gs = 0 v, f = 1 mhz 112 pf output capacitance c oss 54 reverse transfer capacitance c rss 40 total gate charge q g v ds = - 4 v, v gs = - 4.5 v, i d = - 0.8 a 1.7 3.4 nc v ds = - 4 v, v gs = - 2.5 v, i d = - 0.8 a 12 gate-source charge q gs 0.3 gate-drain charge q gd 0.4 gate resistance r g f = 1 mhz 1.4 7 14 ? tu r n - o n d e l ay t i m e t d(on) v dd = - 4 v, r l = 5.7 ? i d ? - 0.7 a, v gen = - 4.5 v, r g = 1 ? 10 20 ns rise time t r 15 23 turn-off delaytime t d(off) 14 21 fall time t f 816 tu r n - o n d e l ay t i m e t d(on) v dd = - 4 v, r l = 5.7 ? i d ? - 0.7 a, v gen = - 8 v, r g = 1 ? 510 rise time t r 10 20 turn-off delaytime t d(off) 12 20 fall time t f 714 drain-source body diode characteristics continuous source-drain diode current i s t c = 25 c - 0.3 a pulse diode forward current a i sm - 3 body diode voltage v sd i f = - 0.7 a - 0.8 - 1.2 v body diode reverse recovery time t rr i f = - 0.7 a, di/dt = 100 a/s, t j = 25 c 14 21 ns body diode reverse recovery charge q rr 48nc reverse recovery fall time t a 8 ns reverse recovery rise time t b 6
document number: 67193 s10-2765-rev. a, 29-nov-10 www.vishay.com 3 vishay siliconix SI1315DL new product typical characteristics (25 c, unless otherwise noted) output characteristics on-resistance vs. drain current gate charge 0.0 0.6 1.2 1.8 2.4 3.0 0.0 0.5 1.0 1.5 2.0 v gs =5vthru2.5v v gs =2v v gs =1.5v v gs =1.8v v gs =1v v ds - drain-to-source voltage (v) i d - drain current (a) 0.20 0.28 0.36 0.44 0.52 0.60 0.0 0.6 1.2 1.8 2.4 3.0 v gs =1.8v v gs =2.5v v gs =4.5v r ds(on) - on-resistance ( ) i d - drain current (a) 0.0 0.9 1.8 2.7 3.6 4.5 0.0 0.3 0.6 0.9 1.2 1.5 1.8 i d =0.8a v ds =4v v ds =6.4v v ds =2v q g - total gate charge (nc) v gs - gate-to-source voltage (v) transer characteristics capacitance on-resistance s. junction temperature 0.0 0.1 0.2 0.3 0.4 0.5 0.0 0.3 0.6 0.9 1.2 1.5 t c = 125 c t c = 25 c t c = - 55 c v gs - gate-to-source voltage (v) i d - drain current (a) c rss 0 50 100 150 200 02468 c iss c oss v ds - drain-to-source voltage (v) c - capacitance (pf) 0.7 0.9 1.1 1.3 1.5 - 50 - 25 0 25 50 75 100 125 150 i d =0.8a v gs =4.5v v gs =2.5v t j - junction temperature (c) (normalized) r ds(on) - on-resistance
www.vishay.com 4 document number: 67193 s10-2765-rev. a, 29-nov-10 vishay siliconix SI1315DL new product typical characteristics (25 c, unless otherwise noted) source-drain diode forward voltage threshold voltage 0 0.35 0.70 1.05 1.40 1 0.1 10 t j = 25 c t j = 150 c v sd - source-to-drain voltage (v) i s - source current (a) 0.35 0.45 0.55 0.65 0.75 0.85 - 50 - 25 0 25 50 75 100 125 150 i d = 250 a v gs(th) (v) t j - temperature (c) on-resistance vs. gate-to-source voltage single pulse power, junction-to-ambient 0 0.2 0.4 0.6 0.8 02468 t j =25 c t j = 125 c i d =0.8a r ds(on) - on-resistance ( ) v gs - gate-to-source voltage (v) 0 2 4 6 8 0.001 0.01 0.1 1 10 100 time (s) po w er ( w ) safe operating area, junction-to-ambient 10 0.1 0.1 1 10 1 t a =25 c single pulse 1ms 0.01 1s 10 s, dc 100 limited by r ds(on) * 10 ms 100 ms bvdss limited v ds - drain-to-source voltage (v) * v gs > minimum v gs at which r ds(on) is specified i d - drain current (a)
document number: 67193 s10-2765-rev. a, 29-nov-10 www.vishay.com 5 vishay siliconix SI1315DL new product typical characteristics (25 c, unless otherwise noted) * the power dissipation p d is based on t j(max) = 150 c, using junction-to-cas e thermal resistance, and is more useful in settling the upper dissipation limit for cases where additional heatsinking is used. it is used to determ ine the current rating, when this rating falls below the package limit. current derating* 0.0 0.2 0.4 0.6 0.8 1.0 0 255075100125150 t c - case temperature (c) i d - drain current (a) power, junction-to-case 0.0 0.1 0.2 0.3 0.4 0.5 0 25 50 75 100 125 150 t c - case temperature (c) power (w) power, junction-to-ambient 0.00 0.07 0.14 0.21 0.28 0.35 0 25 50 75 100 125 150 t a - ambient temperature (c) power (w)
www.vishay.com 6 document number: 67193 s10-2765-rev. a, 29-nov-10 vishay siliconix SI1315DL new product typical characteristics (25 c, unless otherwise noted) vishay siliconix maintains worldwide manufacturing capability. products may be manufactured at one of several qualified locatio ns. reliability data for silicon technology and package reliability represent a composite of all qualified locations. for related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?67193 . normalized thermal transient impedance, junction-to-ambient 10 -3 10 -2 1 10 1000 10 -1 10 -4 100 0.2 0.1 0.05 sq u are w a v ep u lse d u ration (s) n ormalized effecti v e transient thermal impedance 1 0.1 0.01 single p u lse t 1 t 2 n otes: p dm 1. d u ty cycle, d = 2. per unit base = r thja =430c/ w 3. t jm -t a =p dm z thja (t) t 1 t 2 4. s u rface mo u nted d u ty cycle = 0.5 0.02 normalized thermal transient impedance, junction-to-foot 1 0.1 0.01 0.2 d u ty cycle = 0.5 sq u are w a v ep u lse d u ration (s) n ormalized effecti v e transient thermal impedance single p u lse 0.1 10 -3 10 -2 1 10 -1 10 -4 0.02 0.05
l b c e e 1 e d e 1 a 2 a a 1 12 0.08 c 3 package information vishay siliconix document number: 71153 06-jul-01 www.vishay.com 1

dim min nom max min nom max a 0.90 ? 1.10 0.035 ? 0.043 a 1 ? ? 0.10 ? ? 0.004 a 2 0.80 ? 1.00 0.031 ? 0.039 b 0.25 ? 0.40 0.010 ? 0.016 c 0.10 ? 0.25 0.004 ? 0.010 d 1.80 2.00 2.20 0.071 0.079 0.087 e 1.80 2.10 2.40 0.071 0.083 0.094 e 1 1.15 1.25 1.35 0.045 0.049 0.053 e 0.65bsc 0.026bsc e 1 1.20 1.30 1.40 0.047 0.051 0.055 l 0.10 0.20 0.30 0.004 0.008 0.012 7 nom 7 nom ecn: s-03946?rev. c, 09-jul-01 dwg: 5549
an813 vishay siliconix document number: 71236 12-dec-03 www.vishay.com 1 single-channel little foot sc-70 3-pin and 6-pin mosfet recommended pad pattern and thermal peformance introduction basic pad patterns this technical note discusses pin-outs, package outlines, pad patterns, evaluation board layout, and thermal performance for single-channel little foot power mosfets in the sc-70 package. these new vishay siliconix devices are intended for small-signal applications where a miniaturized package is needed and low levels of current (around 350 ma) need to be switched, either directly or by using a level shift configuration. vishay provides these single devices with a range of on-resistance specifications and in both traditional 3-pin and new 6-pin versions. the new 6-pin sc-70 package enables improved on-resistance values and enhanced thermal performance compared to the 3-pin package. pin-out figure 1 shows the pin-out description and pin 1 identification for the single-channel sc-70 device in both 3-pin and 6-pin configurations. the pin-out of the 6-pin device allows the use of four pins as drain leads, which helps to reduce on-resistance and junction-to-ambient thermal resistance. sot-323 sc-70 (3-leads) 1 2 3 top view g s d sot-363 sc-70 (6-leads) 6 4 1 2 3 5 top view d d g figure 1. for package dimensions see outline drawings: sc-70 (3-leads) ( http://www.vishay.com/doc?71153 ) sc-70 (6-leads) ( http://www.vishay.com/doc?71154 ) see application note 826, recommended minimum pad patterns with outline drawing access for vishay siliconix mosfet s, ( http://www.vishay.com/doc?72286 ) for the basic pad layout and dimensions for the 3-pin sc-70 and the 6-pin sc-70. these pad patterns are sufficient for the low-power applications for which this package is intended. increasing the pad pattern has little effect on thermal resistance for the 3-pin device, reducing it by only 10% to 15%. but for the 6-pin device, increasing the pad patterns yields a reduction in thermal resistance on the order of 35% when using a 1-inch square with full copper on both sides of the printed circuit board (pcb). the availability of four drain leads rather than the traditional single drain lead allows a better thermal path from the package to the pcb and external environment. evaluation boards for the single sc70-3 and sc70-6 figure 2 shows the 3-pin and 6-pin sc-70 evaluation boards (evb). both measure 0.6 inches by 0.5 inches. their copper pad traces are the same as described in the previous section, basic pad patterns . both boards allow interrogation from the outer pins to 6-pin dip connections, permitting test sockets to be used in evaluation testing. the thermal performance of the single sc-70 has been measured on the evb for both the 3-pin and 6-pin devices, the results shown in figures 3 and 4. the minimum recommended footprint on the evaluation board was compared with the industry standard of 1-inch square fr4 pcb with copper on both sides of the board. figure 2. front of board sc70-3 front of board sc70-6 back of board, sc70-3 and sc70-6 chipfet chipfet vishay.com
an813 vishay siliconix www.vishay.com 2 document number: 71236 12-dec-03 thermal performance junction-to-foot thermal resistance (the package performance) thermal performance for the 3-pin sc-70 measured as junction-to-foot thermal resistance is 285 c/w typical, 340 c/w maximum. junction-to-foot thermal resistance for the 6-pin sc70-6 is 105 c/w typical, 130 c/w maximum ? a nearly two-thirds reduction compared with the 3-pin device. the ?foot? is the drain lead of the device as it connects with the body. this improved performance is obtained by the increase in drain leads from one to four on the 6-pin sc-70. note that these numbers are somewhat higher than other little foot devices due to the limited thermal performance of the alloy 42 lead-frame compared with a standard copper lead-frame. junction-to-ambient thermal resistance (dependent on pcb size) the typical r ja for the single 3-pin sc-70 is 360 c/w steady state, compared with 180 c/w for the 6-pin sc-70. maximum ratings are 430 c/w for the 3-pin device versus 220 c/w for the 6-pin device. all figures are based on the 1-inch square fr4 test board.the following table shows how the thermal resistance impacts power dissipation for the two different pin-outs at two different ambient temperatures. sc-70 (3-pin) room ambient 25 c elevated ambient 60 c p d t j(max) t a r ja p d 150 o c 25 o c 360 o c w p d 347 mw p d t j(max) t a r ja p d 150 o c 60 o c 360 o c w p d 250 mw sc-70 (6-pin) room ambient 25 c elevated ambient 60 c p d t j(max) t a r ja p d 150 o c 25 o c 180 o c w p d 694 mw p d t j(max) t a r ja p d 150 o c 60 o c 180 o c w p d 500 mw note: although they are intended for low-power applications, devices in the 6-pin sc-70 will handle power dissipation in excess of 0.5 w. testing to aid comparison further, figures 3 and 4 illustrate single-channel sc-70 thermal performance on two different board sizes and two dif ferent pad patterns. the results display the thermal performance out to steady state and produce a graphic account of the thermal performance variation between the two packages. the measured steady state values of r ja for the single 3-pin and 6-pin sc-70 are as follows: little foot sc-70 3-pin 6-pin 1) minimum recommended pad pattern (see figure 4) on the evb. 410.31 c/w 329.7 c/w 2) industry standard 1? square pcb with maximum copper both sides. 360 c/w 211.8 c/w the results show that designers can reduce thermal resistance r ja on the order of 20% simply by using the 6-pin device rather than the 3-pin device. in this example, a 80 c/w reduction was achieved without an increase in board area. if increasing board size is an option, a further 118 c/w reduction could be obtained by utilizing a 1-inch square pcb area. time (secs) figure 3. comparison of sc70-3 and sc70-6 on evb thermal resistance (c/w) 0 1 400 80 160 100 1000 240 10 10 -1 10 -2 10 -3 10 -4 10 -5 0.5 in x 0.6 in evb 3-pin 320 time (secs) figure 4. comparison of sc70-3 and sc70-6 on 1? square fr4 pcb thermal resistance (c/w) 0 1 400 80 160 100 1000 240 10 10 -1 10 -2 10 -3 10 -4 10 -5 1? square fr4 pcb 320 6-pin 3-pin 6-pin
application note 826 vishay siliconix document number: 72601 www.vishay.com revision: 21-jan-08 17 application note recommended minimum pads for sc-70: 3-lead 0.022 (0.559) 0.096 (2.438) recommended mi nimum pads dimensions in inches/(mm) 0.025 (0.622) 0.027 (0.686) 0.071 (1.803) 0.045 (1.143) 0.026 (0.648) return to index return to index
legal disclaimer notice www.vishay.com vishay revision: 02-oct-12 1 document number: 91000 disclaimer all product, product specifications and data are subject to change without notice to improve reliability, function or design or otherwise. vishay intertechnology, inc., its affiliates, agents, and employee s, and all persons acting on it s or their behalf (collectivel y, vishay), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any o ther disclosure relating to any product. vishay makes no warranty, repres entation or guarantee regarding the suitabilit y of the products for any particular purpose or the continuing production of any product. to the maximum extent permitted by applicable law, vi shay disclaims (i) any and all liability arising out of the application or use of any product, (ii) any and all liability, including without limitation specia l, consequential or incidental damages, and (iii) any and all i mplied warranties, including warra nties of fitness for particular purpose, non-infringement and merchantability. statements regarding the suitability of products for certain type s of applications are based on vishays knowledge of typical requirements that are often placed on vishay products in generic applications. such statements are not binding statements about the suitability of products for a particular application. it is the customers responsib ility to validate that a particu lar product with the properties descri bed in the product specification is suitable fo r use in a particular application. parameters provided in datasheets and/or specification s may vary in different applications an d performance may vary over time. all operating parameters, including typical pa rameters, must be validated for each customer application by the customers technical experts. product specifications do not expand or otherwise modify vish ays terms and condit ions of purchase, including but not limited to the warranty expressed therein. except as expressly indicate d in writing, vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the vi shay product could result in personal injury or death. customers using or selling vishay products not expressly indicated for use in such applications do so at their own risk. pleas e contact authorized vishay personnel to ob tain written terms and conditions regarding products designed for such applications. no license, express or implied, by estoppel or otherwise, to any intellectual prope rty rights is granted by this document or by any conduct of vishay. product names and markings noted herein may be trad emarks of their respective owners. material category policy vishay intertechnology, inc. hereby certi fies that all its products that are id entified as rohs-compliant fulfill the definitions and restrictions defined under directive 2011/65/eu of the euro pean parliament and of the council of june 8, 2011 on the restriction of the use of certain hazardous substances in electrical and electronic equipment (eee) - recast, unless otherwis e specified as non-compliant. please note that some vishay documentation may still make reference to rohs directive 2002/95/ ec. we confirm that all the products identified as being compliant to directive 2002 /95/ec conform to directive 2011/65/eu. vishay intertechnology, inc. hereby certifi es that all its products that are identified as ha logen-free follow halogen-free requirements as per jedec js709a stan dards. please note that some vishay documentation may still make reference to the iec 61249-2-21 definition. we co nfirm that all the products identified as being compliant to iec 61249-2-21 conform to jedec js709a standards.

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